Semiconductor processing in the fabrication of integrated circuitry typically includes the deposition of layers on semiconductor substrates. One such method is atomic layer deposition (ALD), which involves the deposition of successive monolayers over a substrate within a deposition chamber typically maintained at subatmospheric pressure. With typical ALD, successive monoatomic layers are adsorbed to a substrate and/or reacted with the outer layer on the substrate, typically by the successive feeding of different deposition precursors to the substrate surface.
An exemplary ALD method includes feeding a single vaporized precursor to a deposition chamber effective to form a first monolayer over a substrate received therein. Thereafter, the flow of the first deposition precursor is ceased and an inert purge gas is flowed through the chamber effective to remove any remaining first precursor which is not adhering to the substrate from the chamber. Subsequently, a second vapor deposition precursor, different from the first, is flowed to the chamber effective to form a second monolayer on/with the first monolayer. The second monolayer might react with the first monolayer. Additional precursors can form successive monolayers, or the above process can be repeated until a desired thickness and composition layer has been formed over the substrate.
Present ALD tools and methods include both single wafer depositions and multiple wafer depositions. Single wafer ALD systems suffer from inherent limitations of throughput due to slow deposition rate of the process and in single wafer processing. Multiple wafer depositions employ furnace-type tools which typically retain 200 or more wafers therein for deposition. Accordingly, such have very large reactor volumes typically requiring very long deposition precursor pulse times, as well as purge gas pulse times, which can negate a significant part of the throughput gain in processing multiple wafers at a time. Further, such large reactor volumes create inherent cleaning problems and short cleaning intervals to prevent the peeling of material from the sidewalls of the furnaces which can deposit on the wafers.
While the invention was motivated in addressing the above issues and improving upon the above-described drawbacks, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification, or the drawings), and in accordance with the doctrine of equivalents.